A solid state drive (SSD) is a data storage device that utilizes solid-state memory to retain data in nonvolatile memory chips. NAND-based flash memories are widely used as the solid-state memory storage in SSDs due to their compactness, low power consumption, low cost, high data throughput and reliability. SSDs commonly employ several NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer.
While NAND-based flash memories are reliable, they are not inherently error-free and often rely on error correction coding (ECC) to correct raw bit errors in the stored data. One commonly employed error correction code employed in nonvolatile memory storage modules, such as SSDs, are low-density parity-check (LDPC) codes. An LDPC code is a linear error correcting code having a parity check matrix with a small number of nonzero elements in each row and column. Various methods for decoding data encoded with LDPC error correction codes are known in the art. One commonly employed decoding method for LDPC coding is the layered min-sum algorithm (MSA). While the min-sum algorithm is an approximation of the quasi-optimal decoding method of belief propagation, the layered min-sum algorithm introduces a further hardware simplification. The layered min-sum algorithm is iterative by layer and is based on belief propagation. The layered min-sum algorithm (MSA) is less complex than other decoding methods known in the art. However, the min-sum algorithm exhibits a noticeable degradation in the decoding performance compared to the more complex decoding methods, such as belief propagation. To counteract the degradation in the decoding performance achievable with the layered min-sum algorithm, normalized layered min-sum algorithms have been developed incorporating a normalization factor, or attenuation factor, to account for the degradation in decoding performance.
The power of LDPC codes resides in the ability of the decoding strategy to exploit the soft information on the stored data. In LDPC decoding, the two voltage distributions represent the two possible states: “0” and “1”, of the cells within the NAND chips. Soft information for the stored data is expressed by a log likelihood ratio (LLR). The read errors are not binary in nature, but instead vary from an ideal voltage according to an analog function. LDPC decoders have the ability to address this non-binary behavior using LLRs. The LLR attributed to a bit is representative of the probability that the voltage value read corresponds to a 0 or a 1. The sign of the LLR typically provides the bit estimation (i.e. positive LLR corresponds to 0 and negative LLR corresponds to 1). The magnitude of the LLR provides the reliability of the estimation (i.e. |LLR|=0 means that the estimation is completely unreliable and |LLR|=∞ means that the estimation is completely reliable and the bit value is known).
Reading soft information from the NAND chips requires multiple reads at varying reference voltages. Performing multiple reads is time consuming and has a severe negative impact on the performance of the flash memory controller. As such, it is desirable to reduce the number of reads required to obtain quality LLR data that will be useful in the decoding process.
Accordingly, what is needed in the art is an improved system and method for higher quality log likelihood ratio (LLRs) to be used in the decoding of LDPC encoded.